46 English-speaking jobs in Catania

The CMMS Maintenance Planner – Ultra Pure Water (UPW) Systems develops and maintains preventive maintenance plans for UPW systems using the Limble CMMS. This role coordinates maintenance schedules, analyzes data, and prepares reports. The ideal candidate has a Bachelor's degree in Engineering, 1-2 years of experience in developing preventive maintenance plans, and experience with CMMS, ERP systems, and data management tools.

Senior Analog Layout Engineer leads chip and block level layout for high-performance analog and mixed-signal products. Responsibilities include floorplan activities, power supply strategy, and driving top-level integration. Requires 10+ years of experience leading analog layout activities in complex ICs, fluency in English, and expertise in layout design tools.

Support system and infrastructure operations for space and defense programs. Administer Linux (RedHat-based), VMware, and OpenStack environments. Perform system management, monitoring, and automation tasks. 2-4 years of experience required. B1/B2 English proficiency needed.

Develop digital sub-circuits for System-on-Chip (SoC) based on specifications. Expertise in Verilog/SystemVerilog, synthesis, STA, formal verification, and power analysis required. Collaborate with analog, mixed-signal, and software teams. Contribute to design for testability (DFT) implementation and verification. Generate design documentation and participate in post-silicon validation.

Tecnimont seeks a Civil & Structural Materials & Work Quantities Estimating & Management Specialist to provide integrated solutions for complex plants. The role involves estimating materials and works, issuing accounting documents, and ensuring deliverables meet contractual and company standards.

Ground Segment Monitoring Technician to support the FLEX mission within a major European space program. Monitor Ground Segment systems, detect issues, and ensure smooth data flow. 2-3 years of experience in systems or service monitoring required. B2 level English proficiency needed. Relocation to Rome is mandatory.

Support the development and optimization of advanced power semiconductor technologies and packaging solutions for automotive and industrial applications. Develop and validate electrical and electro-thermal models for power dies, packages, and modules. Contribute to system-level simulations for power electronics applications. Collaborate with package, device, and system engineering teams to optimize electrical and thermal performance. Analyze thermal behavior, switching performance, parasitic effects, and power losses in semiconductor packages and modules. Support the development of simulation methodologies and model validation flows. Contribute to laboratory validation activities and test setup definition. Support the evaluation of new package technologies and power module architectures for SiC and GaN applications. Collaborate with cross-functional teams including R&D, reliability, manufacturing, and application engineering.

Support test improvement activities for high-frequency characterization of power MOSFETs and IGBTs. Set up and optimize a measurement system for intrinsic device capacitances using S-parameters. Measure S-parameters, extract capacitances, and investigate frequency dependence. Analyze measurement conditions and compare results with device models. Prepare technical documentation.

Senior DFT Designer to develop and implement DFT architectures for complex SoCs. Responsibilities include scan insertion, test compression, memory BIST, and collaboration with cross-functional teams. Requires expertise in DFT methodologies, ATPG tools, UPF/CPF-based DFT, and scripting languages.

The Expediter monitors material supply progress, ensuring adherence to contractual dates and methods. The role involves collaborating with suppliers, technical functions, and procurement to track supply chain activities and identify potential issues. The Expediter also generates reports, analyzes expediting data, and coordinates with internal teams to ensure timely delivery of materials.

This internship focuses on developing and validating a robust measurement methodology for junction-to-case thermal resistance (Rth) on power packages. Interns will perform electrical and thermal measurements, analyze test conditions, and propose an optimized measurement procedure.

Staff Analog Engineer will design and develop smart power stages and power management ICs. Responsibilities include circuit design, simulation, analysis, and collaboration with cross-functional teams. Requires a BSEE (8+ years), MSEE (6+ years), or Ph.D. (3+ years) in analog and mixed-signal IC design.

Physical Design Engineer to implement ASIC physical design flow, including floorplanning, placement, routing, and physical verification. Optimize designs for performance, reliability, and manufacturability. Perform chip-level power integrity analysis. Collaborate with global cross-functional teams.

Mixed-Signal Verification Lead ensures high-quality SOC designs. Develops verification strategies, plans, and test cases for mixed-signal systems. Creates functional and AMS models for verification.

Senior DFT Designer to develop and implement DFT architectures for complex SoCs. Responsibilities include scan insertion, test compression, BIST strategies, and collaboration with cross-functional teams. Requires expertise in DFT methodologies, ATPG tools, UPF/CPF-based DFT, and Verilog/SystemVerilog.

Senior Analog IC Design Engineer will design, verify, and validate power management ICs for computing platforms. Responsibilities include transistor-level design, circuit topology evaluation, layout oversight, design documentation, and test support.

Electrical Plant Design Specialist will design electrical systems for complex plants, ensuring documentation quality and compliance with project requirements.

Cloud Engineer to design, develop, and deploy cloud-based systems. Collaborate with teams to evaluate cloud solutions, modify existing systems, and educate on new technologies.

Lead and execute the full digital IC design flow for complex System-on-Chip (SoC) including specification definition, RTL coding, synthesis, STA, formal verification, and power analysis. Collaborate with analog, mixed-signal, and software teams. Mentor junior engineers and contribute to design process improvement.

Food & Beverage Manager needed for Ortea Palace Hotel, Sicily. Plan, organize, and direct all F&B department operations. Ensure customer satisfaction and manage staff performance.