503 English-speaking jobs in Lombardy

  • ZEISS Group
  • Milan
  • September 18
This role combines Global Frame Shape Database Manager and VTO Scan Lab Supervisor duties. Responsibilities include managing frame metadata, supervising the Italian Scan Lab, and ensuring data quality across various platforms. Requires optical expertise and software development knowledge.
  • Bentham Science
  • Lombardy
  • September 17
  • remote work
Section Editor for "Current Surgical Endoscopy" requires a PhD and proven scholarly publishing record. Responsibilities include developing and organizing Topical Issues, coordinating contributors, and promoting the special issue.
  • Appcast
  • Pavia
  • September 17
LogoSenior Principal Engineer to define broadband optical communication IC architectures and technology roadmaps. Requires 15+ years of semiconductor IC development experience and successful broadband optical IC tape-outs.
  • ZEISS Group
  • Lombardy
  • September 17
This role combines Global Frame Shape Database Manager and VTO Scan Lab Supervisor duties. Responsibilities include managing frame shape metadata, supervising the Italian Scan Lab, and ensuring data quality across multiple platforms. Requires optical expertise and software development knowledge.
  • CareerWallet
  • Pavia
  • September 17
LogoTechnical expert leading high-speed digital and mixed-signal IC place-and-route from synthesis to tape-out. Define backend methodologies, drive PPA, SI, and physical verification strategies. Requires 10+ years in digital physical implementation.
  • CareerWallet
  • Pavia
  • September 17
LogoSenior Principal Engineer to define broadband optical communication IC architectures and technology roadmaps. Requires 15+ years of semiconductor IC development experience and successful broadband optical IC tape-outs.
  • CareerWallet
  • Pavia
  • September 17
LogoTechnical leader for HF analog layout strategy for broadband optical or RF ICs. Responsibilities include leading layout architecture, developing methodologies, and mentoring engineers. Requires 10+ years of relevant experience.
  • CareerWallet
  • Pavia
  • September 17
LogoLead R&D for Datacenter Connectivity Silicon, driving innovation for data center, optical networking, and AI infrastructure. Requires 15+ years in semiconductor product development and IC design, with a Master's or PhD.
  • CareerWallet
  • Pavia
  • September 17
LogoSenior Staff Lab Validation Engineer leads bring-up and validation of RF, HF, analog, mixed-signal, and high-speed digital ICs. Responsibilities include developing validation plans, characterizing device performance, and driving root-cause analysis. Requires an Electrical Engineering Master's and 8+ years in semiconductor validation.
  • Appcast
  • Pavia
  • September 17
LogoTechnical expert leading high-speed digital and mixed-signal IC place-and-route from synthesis to tape-out. Define backend methodologies, drive PPA, SI, and physical verification strategies. Requires 10+ years in digital physical implementation.
  • Appcast
  • Pavia
  • September 17
LogoSenior Principal IC Technical Project Leader drives strategic broadband optical communication IC development from concept to production. This role requires 15+ years of semiconductor experience, technical leadership, and advanced CMOS node knowledge.
  • Appcast
  • Pavia
  • September 17
LogoSenior Principal HF Analog Design Engineer to be a company-wide expert in HF analog circuit design for broadband optical communication ICs. Responsibilities include leading high-performance analog and mixed-signal circuit design and establishing design methodologies. Requires 15+ years of analog IC design experience.
  • Appcast
  • Pavia
  • September 17
LogoPrincipal HF Verification Engineer defines verification strategies for broadband optical communication ICs, including mixed-signal interfaces and high-speed digital datapaths. Requires 10+ years of experience and an MSc or PhD in Electrical Engineering.
  • Appcast
  • Pavia
  • September 17
LogoPrincipal HS Digital Design Engineer leads architecture and RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoC products. Requires 10+ years of digital IC design experience and advanced CMOS node knowledge.
  • Appcast
  • Pavia
  • September 17
LogoSenior Staff Lab Validation Engineer leads bring-up and validation of RF, HF, analog, mixed-signal, and high-speed digital ICs. Responsibilities include developing validation plans, characterizing device performance, and driving root-cause analysis. Requires an Electrical Engineering Master's and 8+ years in semiconductor validation.
  • Appcast
  • Pavia
  • September 17
LogoLead R&D for Datacenter Connectivity Silicon, driving innovation for data center, optical networking, and AI infrastructure. Requires 15+ years in semiconductor product development and IC design, with a Master's or PhD.
  • CareerWallet
  • Pavia
  • September 17
LogoPrincipal HF Verification Engineer defines verification strategies for broadband optical communication ICs, including mixed-signal interfaces and high-speed digital datapaths. Requires 10+ years of experience and an MSc or PhD in Electrical Engineering.
  • CareerWallet
  • Pavia
  • September 17
LogoSenior Principal IC Technical Project Leader drives strategic broadband optical communication IC development from concept to production. This role requires 15+ years of semiconductor experience, technical leadership, and advanced CMOS node knowledge.
  • CareerWallet
  • Pavia
  • September 17
LogoPrincipal HS Digital Design Engineer leads architecture and RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoC products. Requires 10+ years of digital IC design experience and advanced CMOS node knowledge.
  • ams Italy S.r.l.
  • Pavia
  • September 17
LogoSenior Principal HF Analog Design Engineer to be a company-wide expert in HF analog circuit design for broadband optical communication ICs. Responsibilities include leading high-performance analog and mixed-signal circuit design and establishing design methodologies. Requires 15+ years of analog IC design experience.
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