84 python English-speaking jobs in Veneto
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Silicon Photonics Design Engineer
- Nokia
- Belluno
- October 16
with optical and RF simulation tools (Lumerical, HFSS, ADS) and photonic circuit design Proficient in Python
Silicon Photonics Design Engineer
- Nokia
- Padua
- October 16
with optical and RF simulation tools (Lumerical, HFSS, ADS) and photonic circuit design Proficient in Python
Silicon Photonics Design Engineer
- Nokia
- Vicenza
- October 16
with optical and RF simulation tools (Lumerical, HFSS, ADS) and photonic circuit design Proficient in Python
Silicon Photonics Design Engineer
- Nokia
- Treviso
- October 16
with optical and RF simulation tools (Lumerical, HFSS, ADS) and photonic circuit design Proficient in Python
SoC/FPGA Engineer
- Nokia
- Verona
- October 16
access to toolchains (Synopsys, Mentor, Cadence) Proficiency in VHDL, Verilog, SystemVerilog; TCL and Python
SoC Physical Design Engineer
- Nokia
- Verona
- October 16
Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk Scripting experience in TCL, Python
SoC/FPGA Engineer
- Nokia
- Venice
- October 16
access to toolchains (Synopsys, Mentor, Cadence) Proficiency in VHDL, Verilog, SystemVerilog; TCL and Python
SoC Physical Design Engineer
- Nokia
- Venice
- October 16
Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk Scripting experience in TCL, Python
SoC/FPGA Engineer
- Nokia
- Rovigo
- October 16
access to toolchains (Synopsys, Mentor, Cadence) Proficiency in VHDL, Verilog, SystemVerilog; TCL and Python
SoC Physical Design Engineer
- Nokia
- Rovigo
- October 16
Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk Scripting experience in TCL, Python
SoC/FPGA Engineer
- Nokia
- Belluno
- October 16
access to toolchains (Synopsys, Mentor, Cadence) Proficiency in VHDL, Verilog, SystemVerilog; TCL and Python
SoC Physical Design Engineer
- Nokia
- Belluno
- October 16
Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk Scripting experience in TCL, Python
SoC/FPGA Engineer
- Nokia
- Padua
- October 16
access to toolchains (Synopsys, Mentor, Cadence) Proficiency in VHDL, Verilog, SystemVerilog; TCL and Python
SoC Physical Design Engineer
- Nokia
- Padua
- October 16
Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk Scripting experience in TCL, Python
SoC/FPGA Engineer
- Nokia
- Vicenza
- October 16
access to toolchains (Synopsys, Mentor, Cadence) Proficiency in VHDL, Verilog, SystemVerilog; TCL and Python
SoC Physical Design Engineer
- Nokia
- Vicenza
- October 16
Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk Scripting experience in TCL, Python
SoC/FPGA Engineer
- Nokia
- Treviso
- October 16
access to toolchains (Synopsys, Mentor, Cadence) Proficiency in VHDL, Verilog, SystemVerilog; TCL and Python
SoC Physical Design Engineer
- Nokia
- Treviso
- October 16
Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk Scripting experience in TCL, Python
Senior Cloud Infrastructure And Network Operations Solutions Architect
- Nvidia
- Rovigo
- October 10
Ubuntu), switch OS internals, security, and HPC/AI traffic patterns Automation and Observability skills: Python
Senior Staff Engineer Analog Mixed-Signal Design (f/m/div)
- Infineon Technologies
- Padua
- September 23
custom IC design flow, and experience with advanced CMOS process nodes (e.g., 130nm–12nm)Skills in Python ... characterization and debugDevelop behavioral and architectural models of ADC and mixed-signal blocks using Python
