7960 design English-speaking jobs in Italy
FPGA DESIGNER
- Digital Recruiting Week
- Pomezia
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Anguillara Sabazia
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Vicovaro
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Magliano Romano
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Anticoli Corrado
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Sambuci
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Tolfa
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Capena
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Fonte Nuova
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Ardea
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Montelibretti
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- San Cesareo
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Lanuvio
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Agosta
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Rocca Priora
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Olevano Romano
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- San Polo dei Cavalieri
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Licenza
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Mandela
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
FPGA DESIGNER
- Digital Recruiting Week
- Albano Laziale
- November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
design in Cities...
- 1507Milan
- 862Rome
- 278Turin
- 241Bologna
- 194Florence
- 146Naples
- 129Genoa
- 96Catania
- 62Bari
- 54Parma
- 51Trento
- 47Venice
- 45Palermo
- 44Modena
- 42Verona
- 39Padua
- 36Pisa
- 32Reggio nell'Emilia
- 31Treviso
- 30Bolzano
- 28Caserta
- 27Varese
- 25Vicenza
- 24Bergamo
- 22Trieste
- 21Monza
- 18Ancona
- 17Como
- 15Brescia
- 15Latina
- 15Lecce
- 14Novara
- 13Ferrara
- 13Reggio Calabria
- 9Savona
- 8Brindisi
- 8Livorno
- 8Perugia
- 8Ravenna
- 7Siena
- 6Pescara
- 6Taranto
- 5Biella
- 5Forlì
- 4Asti
- 4Udine
- 3Giugliano in Campania
- 3Salerno
- 3Syracuse
- 3Terni
- 2Foggia
- 2Messina
- 2Piacenza
- 1Andria
- 1Busto Arsizio
- 1Potenza
- 1Sassari
design in Regions...
- 2259Lombardy
- 1214Lazio
- 615Emilia-Romagna
- 578Veneto
- 560Piedmont
- 357Tuscany
- 261Campania
- 186Sicily
- 180Liguria
- 135Apulia
- 105Trentino-South Tyrol
- 72Friuli–Venezia Giulia
- 59Marche
- 40Calabria
- 39Umbria
- 36Abruzzo
- 28Sardinia
- 4Basilicata
- 4Molise
- 3Aosta Valley
