1217 design English-speaking jobs in Lazio

  • Digital Recruiting Week
  • Vicovaro
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • San Vito Romano
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Mazzano Romano
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Monterotondo
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Gallicano Nel Lazio
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Valmontone
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Palestrina
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Anticoli Corrado
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • San Polo dei Cavalieri
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Capena
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Nemi
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Monte Compatri
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Grottaferrata
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Magliano Romano
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Frascati
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Trevignano Romano
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Olevano Romano
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Santa Marinella
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Colleferro
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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  • Digital Recruiting Week
  • Rocca Priora
  • November 15
, test, integration and validation activities Design methodologies based on the reuse of Intellectual ... Suites (Vivado/Quartus) and state-of-the-art design flows Knowledge of Digital Signal Processing for ... Requirements Programming and Scripting Languages: C/C++, TCL, Python, shell-scripts Knowledge of RTL design ... rules, normative procedures and deadlines Responsible for Hardware and Firmware requirements analysis, design ... code (VHDL, Verilog), pre/post synthesis simulations, Static Timing Analysis Knowledge of Model Based design
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